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AX88180
High-Performance Non-PCI 32-bit 10/100/1000M Gigabit Ethernet Controller
Document No: AX88180/V1.4 Features
High-performance non-PCI local bus 16/32-bit SRAM-like host interface Support big/little endian data bus type Large embedded SRAM for packet buffers 32K bytes for receive buffer 8K bytes for transmit buffer Support IP/TCP/UDP checksum offloads Support interrupt with high or low active trigger mode Highly-integrated Gigabit Ethernet controller Compatible with IEEE802.3, 802.3u, and 802.3ab standards Support 10/100/1000Mbps data rate Support full duplex operation with 1000Mbps data rate Support full and half duplex operations with 10/100Mbps date rate Support 10/100/1000Mbps N-way Auto-negotiation operation Support IEEE 802.3x flow control for full-duplex operation

Support 10/100/1000Mbps data rate with RGMII or MII in 10/100Mbps data rate. Support back-pressure flow control for half-duplex operation Support packet length set by software Support max 4K bytes JUMBO packet Support Wake-on-LAN function by following events Detection of network link-up state Receipt of a Magic Packet Support Magic Packet detection for remote wake-up after power-on reset Support EEPROM interface Support PCMCIA in 16-bit mode Support synchronous or asynchronous mode to host MCU Integrated voltage regulator from 3.3V to 2.5V 2.5V for core and 3.3V I/O with 5V tolerance 128-pin LQFP with CMOS process, RoHS package US patent approved (NO 6799231)
Product Description
The AX88180 is a high-performance and cost-effective non-PCI Gigabit Ethernet controller for various embedded systems including consumer electronics and home network markets that require a higher bandwidth of network connectivity. The AX88180 supports 16/32-bit SRAM-like host interface and Gigabit Ethernet MAC, which is IEEE802.3 10Base-T, IEEE802.3u 100Base-T, and IEEE802.3ab 1000Base-T compatible. The AX88180 supports full-duplex or half-duplex operation at 10/100/1000Mbps speed with auto-negotiation or manual setting. The AX88180 integrates large embedded SRAM for packet buffers to accommodate high bandwidth applications and supports IP/TCP/UDP checksum to offload processing loading from microprocessor/microcontroller in an embedded system
System Block Diagram
Always contact ASIX for possible updates before starting a design. This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
4F, NO.8, Hsin Ann Rd., Hsinchu Science Park, Hsinchu, Taiwan, R.O.C. TEL: 886-3-579-9500 FAX: 886-3-579-9558
Released Date: 5/18/2007 http://www.asix.com.tw
AX88180
Target Applications
Multimedia applications Content distribution application Audio distribution system (Whole-house audio) Video-over IP solutions, IP PBX and video phone Video distribution system, multi-room PVR Cable, satellite, and IP set-top box Digital video recorder DVD recorder/player High definition TV Digital media client/server Home gateway IPTV for triple play Others Printer, kiosk, security system Wireless router & access point
Applications
The AX88180, design with a high-performance RISC CPU, provides a very low cost yet very high-performance embedded networking solution to enable easy and simple LAN or Internet access capability to high-bandwidth multimedia application needs in the Internet era.
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AX88180 Content
1.0 Introduction.........................................................................................................................................................................6 1.1 General Description .......................................................................................................................................................6 1.2 AX88180 Block Diagram...............................................................................................................................................6 1.3 AX88180 Pinout Diagram..............................................................................................................................................7 2.0 Signal Description...............................................................................................................................................................8 2.1 Signal Type Definition ...................................................................................................................................................8 2.2 RGMII/MII Interface .....................................................................................................................................................8 2.3 Host Interface.................................................................................................................................................................9 2.4 EEPROM Interface ......................................................................................................................................................10 2.5 Regulator Interface.......................................................................................................................................................10 2.6 Miscellaneous ..............................................................................................................................................................11 2.7 Power/ground pin.........................................................................................................................................................11 3.0 Functional Description......................................................................................................................................................12 3.1 Host Interface...............................................................................................................................................................12 3.2 System Address Range.................................................................................................................................................12 3.3 TX Buffer Operation ....................................................................................................................................................12 3.4 RX Buffer Operation....................................................................................................................................................12 3.5 Flow Control ................................................................................................................................................................13 3.6 Checksum Offloads and Wake-up ................................................................................................................................13 3.7 Burst-Mode support .....................................................................................................................................................13 3.8 Big/Little-endian support .............................................................................................................................................13 3.9 16-bit Mode..................................................................................................................................................................13 3.10 EEPROM Format.......................................................................................................................................................14 4.0 Register Description .........................................................................................................................................................15 4.1 CMD--Command Register ...........................................................................................................................................16 4.2 IMR--Interrupt Mask Register .....................................................................................................................................16 4.3 ISR--Interrupt Status Register......................................................................................................................................17 4.4 TX_CFG--TX Configuration Register .........................................................................................................................18 4.5 TX_CMD--TX Command Register .............................................................................................................................18 4.6 TXBS--TX Buffer Status Register ...............................................................................................................................18 4.7 TXDES0--TX Descriptor0 Register.............................................................................................................................19 4.8 TXDES1--TX Descriptor1 Register.............................................................................................................................19 4.9 TXDES2--TX Descriptor2 Register.............................................................................................................................20 4.10 TXDES3--TX Descriptor3 Register...........................................................................................................................20 4.11 RX_CFG--RX Configuration Register.......................................................................................................................20 4.12 RXCURT--RX Current Pointer Register ....................................................................................................................21 4.13 RXBOUND--RX Boundary Pointer Register ............................................................................................................21 4.14 MAC_CFG0--MAC Configuration0 Register............................................................................................................21 4.15 MAC_CFG1--MAC Configuration1 Register............................................................................................................21 4.16 MAC_CFG2--MAC Configuration2 Register............................................................................................................22 4.17 MAC_CFG3--MAC Configuration3 Register............................................................................................................23 4.18 TXPAUT--TX Pause Time Register ...........................................................................................................................23 4.19 RXBTHD0--RX buffer Threshold0 Register .............................................................................................................23 4.20 RXBTHD1--RX Buffer Threshold1 Register ............................................................................................................23 4.21 RXFULTHD--RX Buffer Full Threshold Register.....................................................................................................24 4.22 MISC--Misc. Control Register .................................................................................................................................24 4.23 MACID0--MAC ID0 Register ...................................................................................................................................24 4.24 MACID1--MAC ID1 Register ...................................................................................................................................24 4.25 MACID2--MAC ID2 Register ...................................................................................................................................25 4.26 TXLEN--TX Length Register ....................................................................................................................................25 4.27 RXFILTER--RX Packet Filter Register .....................................................................................................................25 4.28 MDIOCTRL--MDIO Control Register ......................................................................................................................26 4.29 MDIODP--MDIO Data Port Register ........................................................................................................................26 4.30 GPIO_CTRL--GPIO Control Register.......................................................................................................................26
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AX88180
4.31 RXINDICATOR--Receive Indicator Register............................................................................................................27 4.32 TXST--TX Status Register .........................................................................................................................................27 4.33 MDCLKPAT--MDC Clock Pattern Register ..............................................................................................................27 4.34 RXCHKSUMCNT--RX IP/UDP/TCP Checksum Error Counter...............................................................................27 4.35 RXCRCNT--RX CRC Error Counter.........................................................................................................................28 4.36 TXFAILCNT--TX Fail Counter .................................................................................................................................28 4.37 PROMDPR--EEPROM Data Port Register ...............................................................................................................28 4.38 PROMCTRL--EEPROM Control Register ................................................................................................................28 4.39 MAXRXLEN--Max. RX Packet Length Register......................................................................................................29 4.40 HASHTAB0--Hash Table0 Register ..........................................................................................................................29 4.41 HASHTAB1--Hash Table1 Register ..........................................................................................................................29 4.42 HASHTAB2--Hash Table2 Register ..........................................................................................................................29 4.43 HASHTAB3--Hash Table3 Register ..........................................................................................................................29 4.44 DOGTHD0--Watch Dog Timer Threshold0 Register ...............................................................................................30 4.45 DOGTHD1--Watch Dog Timer Threshold1 Register ...............................................................................................30 4.46 SOFTRST --- Software Reset Register ......................................................................................................................30 5.0 Electrical Specification and Timings ................................................................................................................................31 5.1 DC Characteristics .......................................................................................................................................................31 5.1.1 Absolute Maximum Ratings..................................................................................................................................31 5.1.2 General Operation Conditions .............................................................................................................................31 5.1.3 Leakage Current and Capacitance.......................................................................................................................31 5.1.4 DC Characteristics of 2.5V IO Pins .....................................................................................................................31 5.1.5 DC Characteristics of 3.3V IO Pins .....................................................................................................................32 5.1.6 Power Consumption .............................................................................................................................................32 5.1.7 Thermal Characteristics.......................................................................................................................................32 5.2 A.C. Timing Characteristics .........................................................................................................................................33 5.2.1 Host Clock ............................................................................................................................................................33 5.2.2 Reset Timing .........................................................................................................................................................33 5.2.3 Host Single Write Timing......................................................................................................................................33 5.2.4 Host Burst Write Timing .......................................................................................................................................34 5.2.5 Host Single Read Timing ......................................................................................................................................34 5.2.6 Host Burst Read Timing........................................................................................................................................35 5.2.7 RGMII Clock Timing ............................................................................................................................................35 5.2.8 RGMII Receive Timing (1000/100/10 Mbps)........................................................................................................36 5.2.9 RGMII Transmit Timing .......................................................................................................................................36 5.2.10 MDIO Timing .....................................................................................................................................................37 5.2.11 Serial EEPROM Timing......................................................................................................................................37 6.0 Package Information .........................................................................................................................................................38 7.0 Ordering Information........................................................................................................................................................39 Appendix A1. Appendix A2. Appendix A3. Appendix A4. Appendix A5. 16-bit mode address and data bus...............................................................................................................40 32-bit mode address and data bus...............................................................................................................42 AX88180 with Giga-PHY Connection.......................................................................................................43 Synchronous and asynchronous timing selection.......................................................................................44 Wake On LAN (WOL) without driver via Magic Packet...........................................................................45
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AX88180
Revision History .....................................................................................................................................................................46
List of Figures
Figure 1 : AX88180 block diagram ...................................................................................................................................... 6 Figure 2 : AX88180 pin connection diagram........................................................................................................................ 7 Figure 3: 32-bit mode address mapping................................................................................................................................ 12 Figure 4: data swap block ..................................................................................................................................................... 13 Figure 5: 16-bit mode memory mapping .............................................................................................................................. 14
List of Tables
Table 1 : RGMII/MII Interface signals group ...........................................................................................................................8 Table 2 : Host Interface signals group ......................................................................................................................................9 Table 3 : EEPROM Interface signals group............................................................................................................................10 Table 4 : Regulator signals group ...........................................................................................................................................10 Table 5 : Miscellaneous signals group ....................................................................................................................................11 Table 6 : Power/Ground pins group ........................................................................................................................................11 Table 7: MAC Register Mapping............................................................................................................................................15
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AX88180
1.0 Introduction
1.1 General Description
The AX88180, SRAM-like 16/32-bit local bus to Gigabit Ethernet bridge, supports a 10/100/1000 Mbps with RGMII (V2.0 in delay timing) or MII in wire-speed operation. AX88180 supports RGMII (802.3ab, 1000Base-T) interface with full-duplex operation at gigabit speed and full-duplex or half-duplex operation at 10/100 Mbps speed. AX88180 can also operate in MII mode with 10/100Mbps speed. The AX88180 has two built-in synchronous SRAM for buffering packet. The one is 32K bytes for receiving packets from Ethernet PHY; the other is 8K-bytes for transmitting packets from host system to Ethernet PHY. The AX88180 also has 256 bytes built-in configuration registers. For software programming, the total address space used in AX88180 is 64K in 32-bit mode and at least (8K + 8) bytes in 16-bit mode. Because AX88180 is a SRAM-like device, AX88180 could be treated as a SRAM device and can be attached to SRAM controller of system. Therefore, system can execute DMA cycles to gain the highest performance. AX88180 needs 2 clock sources. One (HCLK) is the same to host system clock or from stand-along OSC, the other is 125Mhz (CLK125) for AX88180 running in RGMII mode. In general application, the 125MHz clock can be from Giga -PHY for cost effectively.
1.2 AX88180 Block Diagram
Figure 1 : AX88180 block diagram
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AX88180
1.3 AX88180 Pinout Diagram
The AX88180 is housed in the 128-pin LQFP package.
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 VCC25 GND NC NC GND NC TEST5 VCC25 TEST4 GND GND VCC25 TEST3 TEST2 GND VCC25 COL CRS VCC25 RXD3 RXD2 RXD1 RXD0 GND VCC25 RXCLK RXDV TXCLK TXCX GTXCLK TXEN TXD0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VCC33 HD14 HD13 VCC25 HD12 HD11 HD10 GND HD9 HD8 HD7 HD6 VCC33 HD5 HD4 HD3 HD2 HD1 HD0 VCC25 HA15 HA14 HA13 HA12 HA11 HA10 VCC25 HA9 HA8 HA7 HA6 HA5
TEST6 VCC25 GND VCC25 GND INTN RST_N HCLK VCC33 GND VCC25 HD31 HD30 HD29 HD28 HD27 HD26 HD25 WAKEUP HD24 VCC25 HD23 VCC33 HD22 HD21 HD20 VCC25 HD19 HD18 HD17 HD16 HD15
AX88180
non-PCI 16 / 32 bit Gigabit Ethernet Controller
VCC25 TXD1 TXD2 TXD3 VCC25 MDIO MDC VCC25 GND GPIO0 GPIO1 TEST1 TEST0 CLK125 EEDO EEDI EECS EECLK PHYINTN CSN WEN OEN HA1 HA2 VCC33 REG_EN V25OUT VCC33R GNDR VCC25 HA3 HA4
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Figure 2 : AX88180 pin connection diagram
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AX88180
2.0 Signal Description
2.1 Signal Type Definition
I3: I2: I25 O3: O2: IO3: IO2: TSO: OD: PD: PU: GND: VCC3: VCC2: I: O: IO: Input, 3.3V with 5V tolerance Input, 2.5V with 3.3V tolerance Input 2.5V only Output, 3.3V Output, 2.5V Input/Output, input 3.3V with 5V tolerance Input/Output, input 2.5V with 3.3V tolerance Tri-State Output Open Drain allows multiple devices to share as a wire-OR Internal 75K Pull Down Internal 75K Pull Up Digital Ground 3.3V power 2.5V power Input only Output only Input/Output
2.2 RGMII/MII Interface
Table 1 : RGMII/MII Interface signals group
Pin Name Type CLK125 TXEN I3 Pin NO 51 Pin Description Free running clock 125MHz from OSC or Giga-PHY.
Transmit Enable: TXEN is transition synchronously with respect to the rising and falling edge of TXCX. TXEN indicates that the port is presenting nibbles on TXD [3:0] for transmission. TXD[3:0] O2, 12mA 61,62,63,65 Transmit Data: TXD[3:0] is transition synchronously with respect to the rising and falling edge of TXCX. In rising edge TXD[3:0] is as general TD[3:0] and falling edge TXD[3:0] is as TD[7:4]. TD[7:0] is used in AX88180 as byte unit. TXCX O2, 12mA 68 125MHz Clock Output: It is a continuous 125 MHz clock Output to Giga-PHY operating in RGMII mode. It is a timing reference for TXEN and TXD[3:0]. For normal operation, this pin will be connected to Giga-PHY. GTXCLK O2, 12mA 67 125MHz Clock Output: It is a continuous 125 MHz clock output. This pin is for internal debug purpose only and should be floating for normal operation. RXCLK I2 71 Receive Clock: RXCLK is a continuous clock that provides the timing reference for RXDV, RXD[3:0]. This clock is provided from PHY. RXD[3:0] I2 77,76,75,74 Receive Data: RXD[3:0] is driven by the PHY synchronously with respect to RXCLK. In rising edge RXD[3:0] is as RD[3:0] and falling edge is as RD[7:4]. RD[7:0] is used in AX88180 as byte unit. RXDV I2 70 Receive Data Valid: RXDV is driven by the PHY synchronously with respect to RXCLK in rising and falling edge. It is asserted high when valid data is present on RXD [3:0]. COL I2 80 Collision: This signal is driven by PHY when collision is detected. CRS I2 79 Carrier Sense:
O2, 12mA 66
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AX88180
MDIO IO2, PU, 8mA O2, 8mA 59 Asynchronous signal CRS is asserted by the PHY when either the transmitted or receive medium is non-idle. Station Management Data Input /Output: Serial data input/Output transfers from/to the PHY. The transfer protocol conforms to the IEEE 802.3u MII specification. Station Management Data Clock: The timing reference for MDIO. All data transfers on MDIO are synchronized to the rising edge of this clock. Interrupt signal from PHY, active low. A clock from Giga-PHY operates in MII mode. If Giga-PHY provides clock for 10/100M in MII mode, AX88180 can use this pin as reference clock. For normal operation, to connect TXCLK of Giga-PHY with this pin.
MDC
58
PHYINTN I2 TXCLK I2
46 69
2.3 Host Interface
Table 2 : Host Interface signals group
Pin Name INTN Type TSO, 8mA Pin NO 102 Pin Description Interrupt to host system When the polarity is active high, this signal must be pulled low, otherwise pulled high in active low environment. Software set the bit6 of command register (CMD) to response the polarity. Reset signal: active low. Reference Clock. This clock may be from host (synchronous mode) or the output of stand-alone OSC (asynchronous mode). Wake-up signal to system. When the polarity of system is active high, this signal must be pulled low, otherwise pulled high in active low environment. Software set the bit0 of command register (CMD) to response the polarity. Data bus bit0. Data bus bit1. Data bus bit2. Data bus bit3. Data bus bit4. Data bus bit5. Data bus bit6. Data bus bit7. Data bus bit8. Data bus bit9. Data bus bit10. Data bus bit11. Data bus bit12. Data bus bit13. Data bus bit14. Data bus bit15. Data bus bit16, internal pull down. * Data bus bit17, internal pull down. * Data bus bit18, internal pull down. * Data bus bit19, internal pull down. * Data bus bit20, internal pull down. * Data bus bit21, internal pull down. * Data bus bit22, internal pull down. * Data bus bit23, internal pull down. * Data bus bit24, internal pull down. * Data bus bit25, internal pull down. *
RST_N HCLK WAKEUP
I3 I3 TSO, 8mA
103 104 115
HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25
IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA
19 18 17 16 15 14 12 11 10 9 7 6 5 3 2 128 127 126 125 124 122 121 120 118 116 114
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AX88180
HD26 HD27 HD28 HD29 HD30 HD31 HA1 HA2 HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 WEN CSN OEN IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA IO3, 8mA I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 113 112 111 110 109 108 42 41 34 33 32 31 30 29 28 26 25 24 23 22 21 44 45 43 Data bus bit26, internal pull down. * Data bus bit27, internal pull down. * Data bus bit28, internal pull down. * Data bus bit29, internal pull down. * Data bus bit30, internal pull down. * Data bus bit31, internal pull down. * Address bus bit1. Address bus bit2. Address bus bit3. Address bus bit4. Address bus bit5. Address bus bit6. Address bus bit7. Address bus bit8. Address bus bit9. Address bus bit10. Address bus bit11. Address bus bit12. Address bus bit13. Address bus bit14. Address bus bit15. Data Write Enable: Host drives WEN and it is active low. Chip Select Enable. Host drives CSN and it is active low. Data Output Enable: Host drives OEN and it is active low.
*Note: The internal Pull-down of HD16 to HD31 will be disabled in 32-bit mode.
2.4 EEPROM Interface
Table 3 : EEPROM Interface signals group
Pin Name EECLK EECS EEDI EEDO Type O3, 12mA O3, 12mA O3, 12mA I3, PD Pin No. 47 48 49 50 Pin Description A low speed clock to EEPROM Chip select to EEPROM device. Data to EEPROM, valid in EECS is high and EECLK in rising edge. Data from EEPROM
2.5 Regulator Interface
Table 4 : Regulator signals group
Pin Name VCC33R GNDR REG_EN V25OUT Type VCC3 GND I3 O2 Pin No. 37 36 39 38 Pin Description 3.3V power to internal regulator Ground pin for internal regulator High to enable internal regulator. Low to disable internal regulator. 2.5V output from internal regulator, max 250mA, when REG_EN pin is high.
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2.6 Miscellaneous
Table 5 : Miscellaneous signals group
Pin Name GPIO0 Type IO3, 12mA, PD IO3, 12mA, PD I3, PD I3, PD I25 I25 I25 I25 I25 O Pin No. Pin Description 55 General Purpose pin. In reset stage this pin defines chip operates in 16 or 32-bit mode. Pull-down is for 32-bit mode and pull-up (by 4.7K) is for 16-bit mode. If this pin is floating, it will be as default for 32-bit mode. General Purpose pin. In reset stage this pin defines chip operates in little-endian or big-endian mode. Pull-down is little-endian mode and pull-up is big-endian mode. If this pin is floating, it will as default for little-endian mode. Connect to ground for normal operation. Connect to ground for normal operation. Connect to ground for normal operation. Connect to ground for normal operation. Pull-down for normal operation Connect to ground for normal operation. Pull-up (with 4.7K) for normal operation
GPIO1
54
TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 NC
52 53 83 84 88 90 97
91,93,94 No connection
2.7 Power/ground pin
Table 6 : Power/Ground pins group
Pin Name VCC33 VCC25 GND Type VCC3 VCC2 GND Pin No. 1,13,40, 105, 119 4,20,27,35,57,60,64,72,78,81,85,89,96,98,100,107, 117,123 8,56,73,82,86,87,92,95,99,101,106 Pin Description 3.3V power pins 2.5V power pins Ground pins
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3.0 Functional Description
3.1 Host Interface AX88180 supports a very simple SRAM-like interface. There are only 3 control signals to operate the read or write. For write operation, host activates CSN and WEN to low with address and data bus. AX88180 will decode and latched the data into internal buffer. For normal operation, the WEN needs at least 4 clocks duration for one 32/16-bit write operation. The CSN can always be driven, but WEN must at least be de-asserted 1 clock before next access. For read operation, host asserts CSN and OEN at least 5 clocks to AX88180, the data will be valid after 4 clocks. AX88180 also support burst mode if host reads/writes AX88180 by continuous access. Note: The burst mode only supports in TX/RX, not supports in registers read/write. That is, reads RX area from XXXX_0000 to XXXX_7FFF or writes TX area from XXXX_8000 to XXXX_FBFF can be accessed by burst mechanism. 3.2 System Address Range AX88180 is suitable to attach to SRAM controller, so it needs 64K memory space for operation. The designer can allocate any block (64K) in system space. From offset 0x0000 to 0x7FFF is for RX operation, and offset 0x8000 to 0xFBFF is for TX operation. The internal configuration register of AX88180 is allocated in offset 0xFC00 to 0xFCFF. Below is the mapping of addressing.
31
0
X X X X _0000h
R X a re a 3 2 7 6 8 b y te s
X X X X _8000h T X a re a 3 1 7 4 4 b y te s
R e g is te rs a re a 2 5 6 b y te s N o u se d a re a 7 6 8 b y te s
X X X X _FC 00h X X X X _FD 00h X X X X _FFFFh
Figure 3: 32-bit mode address mapping
3.3 TX Buffer Operation AX88180 employs 4 descriptors to maintain transmit information, such as packet length, start bit. These descriptors are located in offset 0xFC20, 0xFC24, 0xFC28 and 0xFC2C. Driver can choose any descriptor whenever there is data needed to be transmitted. Since there are only 4 descriptors, upon running out of descriptors, driver must wait for the descriptor is to be released by AX88180. 3.4 RX Buffer Operation AX88180 is built a 32K SRAM for RX operation. It utilizes ring structure to maintain the input data from PHY and read out to host. There are two pointer registers located in offset 0xFC34 and oxFC38. AX88180 will maintain RXCURT register. Upon it receives a valid packet from PHY it will update RXCURT according to the packet length. Driver reads data from AX88180 and maintains the RXBOUND register. When driver finishes reading packet, it must update RXBOUND according to the packet length. AX88180 utilizes RXCURT and RXBOUND to provide receive buffer status, full or empty.
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3.5 Flow Control In full duplex mode, AX88180 supports the standard flow control mechanism defined in IEEE 802.3x standard. It enables the stopping of remote node transmissions via a PAUSE frame information interaction. When space of the packet buffer is less than the threshold values (RXBTHD0, RXBTHD1), AX88180 will send out a PAUSE-ON packet to stop the remote node transmission. And then AX88180 will send out a PAUSE-OFF packet to inform the remote node to retransmit packet if it has enough space to receive packets. 3.6 Checksum Offloads and Wake-up To reduce the computing loading of CPU, AX88180 is built checksum operator for IP, UDP or TCP packet. AX88180 will detect the packet whether it is IP, UDP or TCP packet. If it is an IP packet, AX88180 will calculate the checksum of header and put the result in checksum filed of IP. Then it continuously checks the packet whether it is UDP or TCP. It will perform the checksum operation whenever it is a UDP or TCP packet. AX88180 also automatically skip the VLAN tag when checksum is executed. AX88180 also supports to detect magic packet or link-up to wake up system when system is in sleep state or needs to cold start by magic packet. 3.7 Burst-Mode support To improve the throughput in embedded system, AX88180 supports fast-mode (burst) for TX/RX buffer access. Host can access AX88180 by driving CSN to low and toggle WEN (write) or OEN (read). AX88180 can support the burst until whole packet access. The access timing can refer to section 5.2.4 and 5.2.6. This mechanism is only for TX/RX buffer access. For configuration register access, it must use single access. 3.8 Big/Little-endian support AX88180 supports "Big" or "Little" endian data format. The default is Little-endian. Designer can pull-up GOIO1 pin to high to swap the data format. Below table can depict the relation. This swap is only valid in 32-bit mode.
D [3 1 :2 4 ]
D [2 3 :1 6 ]
D [1 5 :8 ]
D [7 :0 ]
L ittle -e n d ia n
D [7 :0 ]
D [1 5 :0 ]
D [2 3 :1 6 ]
D [3 1 :2 4 ]
B ig -e n d ia n
Figure 4: data swap block 3.9 16-bit Mode AX88180 also supports 16-bit mode operation. AX88180 driver should request at least (8K + 8) bytes space for TX, RX and register access. For example, the driver requests a 16K bytes space from system and then sets the new window base address to MEMBAS6 register. After that, driver should set bit 0 (DECODE_EN) of MEMBASE register to start decoding for TX buffer, RX buffer and registers access. (Note: AX88180 H/W only decodes low 16-bit offset address.)
MEMBASE--Memory base Address
Field Name 15:1 0 DECODE_EN Type Default R/W R/W 0 Description Reserved. The output value is undefined if software read this field. 16-bit decode enable Set to `1' to start decoding.
MEMBAS6--Memory base Address + 6
Description Reserved. The output value is undefined if software read this field. 0x00 Window Base Pointer. (The MSB of new window base address, 16-bit offset) This field defines another new windows base address for TX, RX and register access. The total size is 8K bytes. TX areas occupy 3840 bytes Registers occupy 256 bytes. RX areas occupy 4096 bytes. Note: The WINSIZE field of this address is used to define the MSB of new window base address, the TX buffer, RX buffer and registers should be accessed through this new window base address in 16-bit mode. Please refer to below mapping mechanism for details. 15:8 7:0 WINSIZE R/W R/W Field Name Type Default
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15 MEMBASE
0
Base address (xx_0000) Base address + 6 (xx_0006) Set MEMBAS6 = 0x0010
New window base address (xx_1000) TX buffer area (3840 bytes) Registers area (256 bytes) RX buffer area (4096 bytes) Figure 5: 16-bit mode memory mapping The following is an example to indicate how to define a new window base address in 16-bit mode by configuring the MEMBAS6 register. If AX88180 is allocated at the memory base address 0x20_0000 by hardware (i.e. the MEMBASE register is allocated at 0x20_0000) and users would like to set the new window base address to 0x20_1000, the driver should write 0x0010 to the MEMBAS6 register (offset 0x20_0006). In this case, the TX buffer area will be allocated from 0x20_1000 to 0x20_1EFF; the registers area will be allocated from 0x20_1F00 to 0x20_1FFF and the RX buffer area will be allocated from 0x20_2000 to 0x20_2FFF. (Note: AX88180 only decodes low 16-bit address) 3.10 EEPROM Format AX88180 will auto-load data from EEPROM device after hardware reset. If the EEPROM device is not attached, the loading operation will be discarded. The EEPROM mainly provides MAC address information and CIS information if it is used in PCMCIA environment. Below table is the format if EEPROM device is employed. Note: If the MAC address is 12 34 56 78 9A BC (MSB-LSB) then driver should set MACID0=0x9ABC, MACID1=0x5678 and MACID2=0x1234. Address 0 16-bits data Description Pointer to starting address of CIS area. Set this field to 0x0070 to shorten the download EEPROM if there is no CIS needed. AX88180 only supports the 16-bit mode of 93C56, thus the max value of this field is 0x007F. This field should not be set to 0x0000 or 0xFFFF; otherwise, AX88180 will not recognize the EEPROM during hardware reset. MACID0 data MACID1 data MACID2 data Reserved, keep all 0's Bit0: When GPIO0 is set to `1' in reset stage, this bit indicates AX88180 whether it is in the environment of PCMCIA. 0 = General 16-bit mode, 1= Special for PCMCIA environment of 16-bit mode. Bit1: must be `0' Bit2: 1 = set RGMII mode by EEPROM, 0 = none. (The setting will be cleared when software resets) Bit3: 1 = set Gigabit mode by EEPROM, 0=none (The setting will be cleared when software resets) Others bits must set to 0s Reserved, keep all 0's CIS area, if AX88180 is used in PCMCIA system, otherwise set them to all `0s' RX buffer area (xx_2000 ~ 2FFF) TX buffer area (xx_1000 ~ 1EFF) Registers area (xx_1F00 ~ 1FFF)
1 2 3 4 5
6 ~ 11 12 ~ 127
14
ASIX ELECTRONICS CORPORATION
AX88180
4.0 Register Description
There are some registers located from 0xFC00 to 0xFCFF. All of the registers are 32-bit boundary alignment, but only low 16-bit are available (exception 0xFC54). For reserved bits, don't set them in normal operation.
Table 7: MAC Register Mapping
Offset Name Description 0xFC00 CMD Command Register 0xFC04 IMR Interrupt Mask Register 0xFC08 ISR Interrupt Status Register 0xFC10 TX_CFG TX Configuration Register 0xFC14 TX_CMD TX Command Register 0xFC18 TXBS TX Buffer Status Register 0xFC20 TXDES0 TX Descriptor0 Register 0xFC24 TXDES1 TX Descriptor1 Register 0xFC28 TXDES2 TX Descriptor2 Register 0xFC2C TXDES3 TX Descriptor3 Register 0xFC30 RX_CFG RX Configuration Register 0xFC34 RXCURT RX Current Pointer Register 0xFC38 RXBOUND RX Boundary Pointer Register 0xFC40 MAC_CFG0 MAC Configuration0 Register 0xFC44 MAC_CFG1 MAC Configuration1 Register 0xFC48 MAC_CFG2 MAC Configuration2 Register 0xFC4C MAC_CFG3 MAC Configuration3 Register 0xFC54 TXPAUT TX Pause Time Register 0xFC58 RXBTHD0 RX Buffer Threshold0 Register 0xFC5C RXBTHD1 RX Buffer Threshold1 Register 0xFC60 RXFULTHD RX Buffer Full Threshold Register 0xFC68 MISC Misc. Control Register 0xFC70 MACID0 MAC ID0 Register* 0xFC74 MACID1 MAC ID1 Register* 0xFC78 MACID2 MAC ID2 Register* 0xFC7C TXLEN TX Length Register 0xFC80 RXFILTER RX Packet Filter Register 0xFC84 MDIOCTRL MDIO Control Register 0xFC88 MDIODP MDIO Data Port Register 0xFC8C GPIO_CTRL GPIO Control Register* 0xFC90 RXINDICATOR Receive Indicator Register 0xFC94 TXST TX Status Register 0xFCA0 MDCLKPAT MDC Clock Pattern Register 0xFCA4 RXCHKSUMCNT RX IP/UDP/TCP Checksum Error Counter 0xFCA8 RXCRCNT RX CRC Error Counter 0xFCAC TXFAILCNT TX Fail Counter 0xFCB0 PROMDPR EEPROM Data Port Register 0xFCB4 PROMCTRL EEPROM Control Register 0xFCB8 MAXRXLEN MAX. RX packet Length Register 0xFCC0 HASHTAB0 Hash Table0 Register* 0xFCC4 HASHTAB1 Hash Table1 Register* 0xFCC8 HASHTAB2 Hash Table2 Register* 0xFCCC HASHTAB3 Hash Table3 Register* 0xFCE0 DOGTHD0 Watch Dog Timer Threshold0 Register 0xFCE4 DOGTHD1 Watch Dog Timer Threshold1 Register 0xFCEC SOFTRST Software Reset Register *Note: It is not affected by software reset Default value 0x0000_0201 0x0000_0000 0x0000_0000 0x0000_0040 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0101 0x0000_0000 0x0000_07FF 0x0000_8157 0x0000_6000 0x0000_0100 0x0000_060E 0x001F_E000 0x0000_0300 0x0000_0600 0x0000_0100 0x0000_0013 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_05FC 0x0000_0004 0x0000_0000 0x0000_0000 0x0000_0003 0x0000_0000 0x0000_0000 0x0000_8040 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0600 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_FFFF 0x0000_0000 0x0000_0003
15
ASIX ELECTRONICS CORPORATION
AX88180
4.1 CMD--Command Register Offset Address = 0xFC00
Field Name 31:16 15 RXVLAN
Default = 0x0000_0201
14
TXVLAN
13:10 9
RXEN
8
TXEN
7 6
INTMOD
5:1 0
WAKEMOD
Type Default Description R/W All 0's Reserved R/W 0 RX VLAN indicator Driver enables this bit to indicate AX88180 that the received packet will include 4 bytes VLAN tag; AX88180 will skip 4 bytes when it calculates the checksum of IP, TCP or UDP packet. 1 = enable 0 = disable R/W 0 TX VLAN indicator Driver enables this bit to indicate AX88180 that the transmitted packet will include 4 bytes VLAN tag; AX88180 will skip 4 bytes when it calculates the checksum of IP, TCP or UDP packet. 1 = enable 0 = disable R/W All 0's Reserved R/W 1 RX Function Enable When this bit is enabled, MAC starts to receive packets. 1 = enable 0 = disable R/W 0 TX Function Enable When this bit is enabled, MAC could start to transmit packet to Ethernet. 1 = enable 0 = disable R/W 0 Reserved R/W 0 Interrupt Active Mode Driver sets this bit to indicate AX88180 the interrupt of system is activated high or low. 1: Active high 0: Active low R/W All 0's Reserved R/W 1 WAKEUP pin polarity Driver sets this bit to indicate AX88180 the polarity of system wake-up signal is activated high or low. 1: Active high 0: Active low
4.2 IMR--Interrupt Mask Register Offset Address = 0xFC04 Default = 0x0000_0000
Field Name 31:6 5 PHYMASK Type Default Description R All 0's Reserved R/W 0 PHY interrupt Mask When this bit is enabled, an interrupt request from PHY set in bit 5 of Interrupt Status Register will make AX88180 to issue an interrupt to host. 1 = enable 0 = disable R/W 0 Packet Received Interrupt Mask When this bit is enabled, a received interrupt request set in bit 4 of Interrupt Status Register will make AX88180 to issue an interrupt to host. 1 = enable 0 = disable R/W 0 Packet Transmitted Interrupt Mask When this bit is enabled, a transmitted interrupt request set in bit 3 of Interrupt Status Register will make AX88180 issue an interrupt to host.
4
PRIM
3
PTIM
16
ASIX ELECTRONICS CORPORATION
AX88180
2 1 DOGIM R/W R/W 0 0 1 = enable 0 = disable Reserved Watch Dog Timer Interrupt Mask When this bit is enabled, a watch dog timer expired interrupt request set in bit1 of Interrupt Status Register will make AX88180 to issue an interrupt to host 1 = enable 0 = disable RX Buffer Full Interrupt Mask When this bit is enabled, a RX buffer full interrupt request set in bit 0 of Interrupt Status Register will make AX88180 to issue an interrupt to host. 1 = enable 0 = disable
0
RXFULIM
R/W
0
4.3 ISR--Interrupt Status Register Offset Address = 0xFC08 Default = 0x0000_0000
Field 31:6 5 Name PHYIG Type R R/W Default All 0's 0 Description Reserved PHY Interrupt Generation If this bit is set to `1', it means there is an interrupt request from PHY. AX88180 will forward this interrupt to system. Meantime driver should poll PHY and adopt proper procedure. Write `1' to this bit to clear this request status. 1 = have interrupt request 0 = no interrupt request Receive Packet Interrupt Generation If this bit is set to `1', it means AX88180 receives a packet or (packets) from PHY. The packet is kept in RX buffer. Write `1' to this bit to clear this request status. 1 = have received packet 0 = no received packet Finish Transmitting Packet Interrupt If this bit is set to `1', it means AX88180 had transmitted packet to PHY. Write `1' to this bit to clear this request status. 1 = finish transmission 0 = none Reserved Watch Dog Timer Expired Interrupt If this bit is set to `1', it means the WATCH DOG timer is expired. AX88180 will issue an interrupt to host. Write `1' to this bit to clear this request status. The expired duration can refer to DOGTHD0 and DOGTHD1 registers. 1 = timer expired happens 0 = none RX Buffer Full Interrupt If this bit is set to `1' it means RX buffer is full and no more packets will be received until packets are read out. Write `1' to this bit to clear this request status. 1 = RX buffer full 0 = None
4
RPIG
R/W
0
3
FTPI
R/W
0
2 1
WDTEI
R/W R/W
0 0
0
RXFULI
R/W
0
17
ASIX ELECTRONICS CORPORATION
AX88180
4.4 TX_CFG--TX Configuration Register Offset Address = 0xFC10 Default = 0x0000_0040
Field Name 31:7 6 TXCRCAP Type R R/W Default Description All 0's Reserved 1 TXCRC Auto-Append When this bit is enabled, AX88180 will append CRC to the transmitted packet in FCS field. 1 = enable 0 = disable 0 Reserved. 0 TX Checksum Generation When this bit is enabled, AX88180 will append checksum to the transmitted packet that is IP or TCP or UDP packet. 1 = enable 0 = disable 00 Reserved 00 TX Description Status AX88180 reports which descriptor is transmitted now Default: 2'b00
5 4
TXCHKSUM
R/W R/W
3:2 1:0
TXDS
R R
4.5 TX_CMD--TX Command Register Offset Address = 0xFC14 Default = 0x0000_0000
Field 31:16 15 Name HWI Type R R/W Default All 0's 0 Description Reserved Host Writes Indication Before host begins to send a packet to TX buffer, this bit should be set. At the end of host writes the packet, this bit should be cleared by software. 1 = Start Writing 0 = End Writing TX Descriptor Pointer To specify which TX descriptor to be written. Reserved Byte Count. Data length is written to transmitted buffer.
14:13 12 11:0
TXDP DATALEN
R/W R/W R/W
00 0 All 0's
4.6 TXBS--TX Buffer Status Register Offset Address = 0xFC18 Default = 0x0000_0000
Field Name 31:4 8 INTXDS Type R R Default All 0's 0 Description Reserved Internal TX descriptor status. This bit reports the TX descriptor status. When there is data to be transmitted, this bit will be set to `1' otherwise it will be `0' 1 = have data in TX buffer 0 = all data are transmitted to PHY Reserved TX Descriptor In Transmitting These status bits indicate which descriptor is transmitting now. 00: Descriptor 0 in transmitting 01: Descriptor 1 in transmitting 10: Descriptor 2 in transmitting 11: Descriptor 3 in transmitting TX Descriptor 3 Occupied Driver set this bit to `1' to indicate that it had used TX descriptor3. When the
7:6 5:4
TXDUSE
R R
00 00
3
TXD3O
R/W
0
18
ASIX ELECTRONICS CORPORATION
AX88180
2 TXD2O R/W 0 transmission is finished, AX88180 will auto-clear this bit. TX Descriptor 2 Occupied Driver set this bit to `1' to indicate that it had used TX descriptor2. When the transmission is finished, AX88180 will auto-clear this bit. TX Descriptor 1 Occupied Driver set this bit to `1' to indicate that it had used TX descriptor1. When the transmission is finished, AX88180 will auto-clear this bit. TX Descriptor 0 Occupied Driver set this bit to `1' to indicate that it had used TX descriptor0. When the transmission is finished, AX88180 will auto-clear this bit.
1
TXD1O
R/W
0
0
TXD0O
R/W
0
4.7 TXDES0--TX Descriptor0 Register Offset Address = 0xFC20 Default = 0x0000_0000
Field 31:16 15 Name TXD0_EN Type R R/W Default All 0's 0 Description Reserved Transmit TX descriptor 0 If this bit is enabled, MAC will begin to transmit data that are stored in TX buffer. In former, driver had already written data that is assigned to TX descriptor0 to TX buffer. This bit will be cleared by hardware when MAC finished the transmission. 1= enable 0= disable Reserved TX packet length (unit: byte) Driver set this field to indicate AX88180 how many bytes will be transmitted.
14:13 12:0
TXD0_LEN
R R/W
00 All 0's
4.8 TXDES1--TX Descriptor1 Register Offset Address = 0xFC24 Default = 0x0000_0000
Field 31:16 15 Name TXD1_EN Type R R/W Default All 0's 0 Description Reserved Transmit TX descriptor 1 If this bit is enabled, MAC will begin to transmit data that are stored in TX buffer. In former, driver had already written data that is assigned to TX descriptor1 to TX buffer. This bit will be cleared by hardware when MAC finished the transmission. 1= enable 0= disable Reserved TX packet length (unit: byte) Driver set this field to indicate AX88180 how many bytes will be transmitted.
14:13 12:0
TXD1_LEN
R R/W
00 All 0's
19
ASIX ELECTRONICS CORPORATION
AX88180
4.9 TXDES2--TX Descriptor2 Register Offset Address = 0xFC28 Default = 0x0000_0000
Field 31:16 15 Name TXD2_EN Type R R/W Default All 0's 0 Description Reserved Transmit TX descriptor 2 If this bit is enabled, MAC will begin to transmit data that are stored in TX buffer. In former, driver had already written data that is assigned to TX descriptor2 to TX buffer. This bit will be cleared by hardware when MAC finished the transmission. 1= enable 0= disable Reserved TX packet length (unit: byte) Driver set this field to indicate AX88180 how many bytes will be transmitted.
14:13 12:0
TXD2_LEN
R R/W
00 All 0's
4.10 TXDES3--TX Descriptor3 Register Offset Address = 0xFC2C Default = 0x0000_0000
Field 31:16 15 Name TXD3_EN Type R R/W Default All 0's 0 Description Reserved Transmit TX descriptor 3 If this bit is enabled, MAC will begin to transmit data that are stored in TX buffer. In former, driver had already written data that is assigned to TX descriptor3 to TX buffer. This bit will be cleared by hardware when MAC finished the transmission. 1= enable 0= disable Reserved TX Packet Length (unit: byte) Driver set this field to indicate AX88180 how many bytes will be transmitted.
14:13 12:0
TXD3_LEN
R R/W
00 All 0's
4.11 RX_CFG--RX Configuration Register Offset Address = 0xFC30 Default = 0x0000_0101
Field 31:9 8 Name RXBME Type R R/W Default All 0's 1 Description Reserved RX Buffer Monitor Enable When this bit is enabled, MAC will monitor the status of receive buffer. 1 = enable 0 = disable Reserved. RX Packet TCP/IP Checksum When this bit is set, AX88180 will check the checksum of the received packet that is IP, TCP or UDP packet. If there is checksum error, AX88180 will drop the packet and RXCHKSUMCNT counter will add 1. 1 = enable 0 = disable Reserved RX Buffer Protection When this bit is enabled, MAC will protect the RX buffer to avoid overrun. For normal operation, this bit should be enabled in initial stage. 1= enable 0= disable
7:5 4
RXCHKSUM
R/W R/W
000 0
3:1 0
RXBUFPRO
R/W R/W
000 1
20
ASIX ELECTRONICS CORPORATION
AX88180
4.12 RXCURT--RX Current Pointer Register Offset Address = 0xFC34 Default = 0x0000_0000
Field 31:11 10:0 Name RXCURPTR Type R R/W Default All 0's All 0's Description Reserved RX Line Current Pointer. Point to the last line that will be written by hardware. The unit of line is 16 bytes. AX88180 will maintain this register.
4.13 RXBOUND--RX Boundary Pointer Register Offset Address = 0xFC38 Default = 0x0000_07FF
Field 31:11 10:0 Name RXBUNPTR Type R R/W Default All 0's 0x7FF Description Reserved RX Line Boundary Pointer. Point to the last line that has been read by driver. The unit of line is 16 bytes. When driver finished reading packet from RX buffer, it must update this field.
4.14 MAC_CFG0--MAC Configuration0 Register Offset Address = 0xFC40 Default = 0x0000_8157
Field 31:16 15 Name SPEED100 Type R R/W Default All 0's 1 Description Reserved Line Speed Mode When this bit is enabled and bit12 of MAC_CFG1 is disabled, MAC will operate in 100Mbps mode otherwise it operates in 10Mbps speed. If bit12 of MAC_CFG1 is enabled, this bit will be ignored Reserved, this bit must set to 0 for normal operation Reserved, this bit must set to 0 for normal operation. RX Flow Control If this bit and bit8 of RX_CFG are enabled, MAC will perform flow control and send pause on/off frame when the available space of receive buffer is less than the value of RXBTHD0. 1 = enable 0 = disable Reserved, this bit must set to 0 for normal operation. Inter Packet Gap (IPG) for 10/100M This field defines the back-to-back transmit packet gap for 10/100M. Inter Packet Gap for 1000M This field defines the back-to-back transmit packet gap for 1000M only.
14 13 12
RXFLOW
R/W R/W R/W
0 0 0
11 10:4 3:0
IPG100 IPG1000
R/W R/W R/W
0 0x15 0x7
4.15 MAC_CFG1--MAC Configuration1 Register Offset Address = 0xFC44 Default = 0x0000_6000
Field 31:15 14 Name PUSRULE Type R R/W Default All 0's 1 Description Reserved Pause Frame Check Rule When this bit is set, AX88180 accepts pause frame that DA can be any value. 1 = don't check DA field. 0 = check DA is equal to "01 80 C2 00 00 01" Check CRC of received Packet. When this bit is enabled, AX88180 will drop any CRC error packet.
13
CRCCHK
R/W
1
21
ASIX ELECTRONICS CORPORATION
AX88180
12 GIGA_EN R/W 0 1 = enable 0 = disable Gigabit Mode Enable When this bit is enabled, MAC will operate in 1000Mbps mode. 1 = enable 0 = disable RX Jumbo Enable When this bit is enabled, MAC will receive jumbo package 1 = enable 0 = disable Length Limit of received Jumbo package This field defines the maximum length of received jumbo package. 0001: 1K bytes 0010: 2K bytes 0011: 3K bytes --------------------1110: 14K bytes 1111: 15K bytes Duplex Mode. 1 = Full-Duplex mode 0 = Half-Duplex mode TX Flow Enable When this bit is enabled, MAC will block the transmitted operation when it captures pause frame from Ethernet. The re-transmission will be activated until the waiting time is expired. 1 = enable 0 = disable Reserved, must set to `0s' for normal operation RGMII Mode Enable When this bit is enabled, AX88180 will operate in RGMII interface. Driver must set external PHY to RGMII mode and enable this bit in initial stage. Driver also must set RGMII interface of external PHY with add-delay timing in its internal. 1 = enable 0 = disable Reserved, must set to `0s' for normal operation
11
RXJUMBO
R/W
0
10:7
RXJUBOLEN R/W
0000
6
DUPLEX
R/W
0
5
TXFLW_EN
R/W
0
4:2 1
RGMIIEN
R/W R/W
000 0
0
-
R/W
0
4.16 MAC_CFG2--MAC Configuration2 Register Offset Address = 0xFC48 Default = 0x0000_0100
Field Name Type Default Description 15:8 R/W 0x01 Reserved, keep this field in default value for normal operation. 7:2 JamLT R/W 000000 Define Jam Limit for backpressure collision account. Normally set this field at 0x19. It can avoid HUB port going to partition state due to too many collisions. AX88180 will skip one frame collision backpressure when collision counter equal to JamLT. The collision count will be reset to zero when every transmit frame with no collision or receive a frame with no backpressure collision. 1:0 R/W 00 Reserved, must set to `00' for normal operation
22
ASIX ELECTRONICS CORPORATION
AX88180
4.17 MAC_CFG3--MAC Configuration3 Register Offset Address = 0xFC4C Default = 0x0000_060E
Field 15 Name NOABORT Type R/W Default 0 Description No Abort When this bit is enabled, MAC will keep retry transmit current frame even excessive collision otherwise it will abort current transmission due to excessive collision. 1 = enable 0 = disable Inter-Frame Gap segment1 Inter-Frame Gap segment2
13:7 6:0
IPGR1 IPGR2
R/W R/W
0001100 0001110
4.18 TXPAUT--TX Pause Time Register Offset Address= 0xFC54 Default = 0x001F_E000
Field 31:23 22:0 Name TXPVAL Type R R/W Default All 0's 0x1F_E000 Description Reserved TX Pause Time out It is used to re-transmit a pause-on frame when pause timer expired and receive buffer still not enough. In 32-bit mode, this field should be set to 0x1F_E000 at 1000Mbps mode and set to 0x7F_8000 at 10/100Mbps modes. In 16-bit mode, this field should be set to 0xFFFF at 10/100/1000Mbps modes. (Note: The bit 16 ~ 22 of this field are invalid in 16-bit mode.)
4.19 RXBTHD0--RX buffer Threshold0 Register Offset Address= 0xFC58 Default = 0x0000_0300
Field 31:11 10:0 Name RXLOWB Type R R/W Default All 0's 0x300 Description Reserved RX Remainder Capacity Low-Bound This field defines as the remainder capacity of RX buffer for pause operation. If the flow control (bit12 of MAC_CFG0) is enabled, MAC will send pause frame when the available space of receive buffer is less than this value. The unit is 16-byte.
4.20 RXBTHD1--RX Buffer Threshold1 Register Offset Address= 0xFC5C Default = 0x0000_0600
Field 31:11 10:0 Name RXHIGHB Type R R/W Default All 0's 0x600 Description Reserved RX Remainder Capacity Upper-Bound This field defines as upper bound of remainder size of RX buffer for pause operation. If the flow control is enabled, MAC will stop to send pause frame until the available space of receive buffer is more than this value. The unit is 16-byte.
23
ASIX ELECTRONICS CORPORATION
AX88180
4.21 RXFULTHD--RX Buffer Full Threshold Register Offset Address= 0xFC60 Default = 0x0000_0100
Field 31:11 10:0 Name RXFULB Type R R/W Default All 0's 0x100 Description Reserved RX Full Threshold This field defines the least capacity of RX buffer. AX88180 will cause RX full if it remains capacity under this value. The unit is 16-byte.
4.22 MISC--Misc. Control Register Offset Address= 0xFC68 Default = 0x0000_0013
Field 31:6 5 Name WAKE_LNK Type R R/W Default Description All 0's Reserved 0 WAKE-UP by Link-Up Function If this bit is enabled, MAC will drive wakeup pin whenever there is link-up occurrence. The polarity of wakeup pin is according to bit0 of CMD register. 1= enable 0= disable 1 WAKE-UP by Magic Packet If this bit is enabled, MAC will drive wakeup pin whenever there is magic packet detected by hardware. The polarity of wakeup pin is according to bit0 of CMD register. 1= enable wake-up by magic packet 0 = disable 00 Reserved 1 Reserved 1 Software Reset MAC core Driver set this bit to `0' to reset core of MAC. The reset duration is depended on whenever this bit is de-asserted by driver. There are only RXCURT and RXBOUND registers will be cleared by this bit. Others registers will not be affected 1 = in normal operation 0 = in reset status
4
WAKE_MAG
R/W
3:2 1 0
SRST_MAC
R/W R/W R/W
4.23 MACID0--MAC ID0 Register Offset Address = 0xFC70 Default = 0x0000_0000
Field 31:16 15:0 Name MID15_0 Type R R/W Default All 0's 0x0000 Description Reserved. MAC ID Address [15:0]. This field defines lower address bit15 to bit0 of MAC. The MACID0, MACID1 and MACID2 combine into 48-bit MAC address. The MAC address format is [47:0] = {MACID2[15:0], MACID1[15:0], MACID0[15:0]}. If the EEPROM is attached, this field will be auto-loaded from EEPROM after hardware reset.
4.24 MACID1--MAC ID1 Register Offset Address = 0xFC74h
Field 31:16 15:0 Name MID31_16 Type R R/W Default All 0's 0x0000
Default = 0x0000_0000
Description
Reserved. MAC ID Address [31:16].
24
ASIX ELECTRONICS CORPORATION
AX88180
4.25 MACID2--MAC ID2 Register Offset Address = 0xFC78 Default = 0x0000_0000
Field 31:16 15:0 Name MID47_32 Type R R/W Default All 0's 0x0000 Description Reserved. MAC ID Address [47:32].
4.26 TXLEN--TX Length Register Offset Address = 0xFC7C Default = 0x0000_05FC
Field 31:11 10:0 Name MAXTXLEN Type R R/W Default All 0's 0x5FC Description Reserved Max TX packet size This field defines the maximum raw packet size in transmittance. It is not included 4 bytes CRC.
4.27 RXFILTER--RX Packet Filter Register Offset Address = 0xFC80 Default = 0x0000_0004
Field 31:6 5 Name GOODCRC Type R R/W Default All 0's 0 Description Reserved Good CRC enable When this bit is enabled, AX88180 will receive any packet of good CRC. 1 = enable 0 = disable Receive Multicast packet by lookup hash table. When this is enabled, AX88180 will receive multicast packet by the hash mapping function. It will refer to HASTAB0, HASHTAB1, HASHTAB2 and HASHTAB3 to look up the table. 1 = enable 0 = disable Receive Broadcast packet When this bit is enabled, AX88180 will receive the broadcast packet 1 = enable 0 = disable Receive Directed Packet. If this bit is enabled, AX88180 will compare the destination address field of received packet with the address of MAC (refer to MACID0, MACID1, MACID2). When it is matched and good CRC, the packet will be passed to driver. Otherwise it will be dropped. 1 = enable 0 = disable Receive all Multicast Packets. If this bit is enabled, any multicast packet (good CRC) will be received and passed to driver. 1 = enable 0 = disable Receive Anything. If this bit is enabled, any packet whether it is good or fail will be received and passed to driver. 1 = enable 0 = disable
4
MULTI_HASH
R/W
0
3
BROADCAST
R/W
0
2
UNICAST
R/W
1
1
MULTICAST
R/W
0
0
RXANY
R/W
0
25
ASIX ELECTRONICS CORPORATION
AX88180
4.28 MDIOCTRL--MDIO Control Register Offset Address = 0xFC84 Default = 0x0000_0000
Field 31:16 15 Name WTEN Type R R/W Default All 0's 0 Description Reserved Write Enable. Driver enables this bit to issue a write cycle to PHY, it will be auto-cleared when AX88180 finishes the write cycle 1 = enable 0 = disable Read Enable. Driver enables this bit to issue a read cycle to PHY. This bit will be auto-cleared when AX88180 finishes the read cycle 1 = enable 0 = disable PHY Register Index Driver sets this field to define the internal register index of PHY when it accesses PHY. Reserved PHY ID Driver sets the PHY ID value in this field. AX88180 will refer to this field when it accesses PHY by MDIO/MDC signals.
14
RDEN
R/W
0
12:8
PHYCRIDX R/W
00000
7:5 4:0
PHYID
R R/W
000 00000
4.29 MDIODP--MDIO Data Port Register Offset Address = 0xFC88 Default = 0x0000_0000
Field 31:16 15:0 Name Type R MDPORT R/W Default Description All 0's Reserved All 0's PHY Data Port To or from PHY data is put in this field.
4.30 GPIO_CTRL--GPIO Control Register Offset Address = 0xFC8C Default = 0x0000_0003
Field 31:10 9 Name GPIO1S Type R R/W Default All 0's 0 Description Reserved GPIO1 Status This bit stands for the pin status of GPIO1 when it is set to input mode. 1 = high state 0 = low state GPIO0 Status This bit stands for the pin status of GPIO0 when it is set to input mode. 1 = high state 0 = low state Reserved GPIO1 Mode Direction This field defines the direction of GPIO1 pin. 1 = input mode 0 = output mode GPIO0 Mode Direction This field defines the direction of GPIO pin. 1 = input mode 0 = output mode
8
GPIO0S
R/W
0
7:2 1
R GPIO1DIR R/W
All 0's 1
0
GPIO0DIR R/W
1
Note: For output mode, software must firstly set the bit0 or bit1 to output mode then set bit8 or bit9.
26
ASIX ELECTRONICS CORPORATION
AX88180
4.31 RXINDICATOR--Receive Indicator Register Offset Address= 0xFC90 Default = 0x0000_0000
Field 31:1 0 Name Type R RXSTART R/W Default All 0's 0 Description Reserved Receive Start Driver sets this bit to start or end receive operation from RX buffer of AX88180. 1= Start read RX buffer 0= End read RX buffer
4.32 TXST--TX Status Register Offset Address = 0xFC94
Field 31:4 3 Name Type R TXD3FAIL R Default All 0's 0
Default = 0x0000_0000
Description Reserved TX Descriptor3 Transmit Fail When this bit is set 1, it means AX88180 fails in transmission of descriptor3. This bit will be self-cleared when driver reads TXST register. TX Descriptor2 Transmit Fail When this bit is set 1, it means A88180 fails in transmission of descriptor2. This bit will be self-cleared when driver reads TXST register. TX Descriptor1 Transmit Fail When this bit is set 1, it means AX88180 fails in transmission of descriptor1. This bit will be self-cleared when driver reads TXST register. TX Descriptor0 Transmit Fail When this bit is set 1, it means AX88180 fails in transmission of descriptor0. This bit will be self-cleared when driver reads TXST register.
2
TXD2FAIL R
0
1
TXD1FAIL R
0
0
TXD0FAIL R
0
4.33 MDCLKPAT--MDC Clock Pattern Register Offset Address = 0xFCA0 Default = 0x0000_8040
Field 31:16 15:8 7:0 Name MDCPAT Type R R/W R/W Default All 0's 0x80 0x40 Description Reserved Reserved, must set to 0x80 for normal operation MDC Clock Divide Factor This field defines the divided factor of host clock. AX88180 will refer to this field and generate a low speed clock to PHY.
4.34 RXCHKSUMCNT--RX IP/UDP/TCP Checksum Error Counter Offset Address = 0xFCA4 Default = 0x0000_0000
Field Name Type 31:16 R 15:0 RXCHKERCNT R/W Default Description All 0's Reserved All 0's RX Checksum Error Counter If the RXCHKSUM field of RX_CFG register is set to `1', MAC will check the checksum of IP, TCP or UDP packet. Whenever there is checksum error detected, this field will be added one. The value will be rounded back to 0x0000 if it exceeds 0xFFFF.
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4.35 RXCRCNT--RX CRC Error Counter Offset Address = 0xFCA8 Default = 0x0000_0000
Field 31:16 15:0 Type R RXCRCCNT R/W Name Default All 0's All 0's Description Reserved RX CRC32 Error Counter MAC checks the received packet. If there is a CRC error detect, this field will be added one. The value will be rounded back to 0x0000 if it exceeds 0xFFFF.
4.36 TXFAILCNT--TX Fail Counter Offset Address = 0xFCAC Default = 0x0000_0000
Field 31:16 15:0 Name Type R TXFILCNT R/W Default All 0's All 0's Description Reserved TX Fail Counter This field records the number of transmitted error for TX packet. The value will be rounded back to 0x0000 if it exceeds 0xFFFF.
4.37 PROMDPR--EEPROM Data Port Register Offset Address = 0xFCB0 Default = 0x0000_0000
Field 31:16 15:0 Name Type R PROMDP R/W Default All 0's All 0's Description Reserved EEPROM Data Port The data to or from EEPROM is set in this field.
4.38 PROMCTRL--EEPROM Control Register Offset Address= 0xFCB4 Default = 0x0000_0000
Field 31:15 14:12 Name Type Default All 0's 000 Description Reserved EEPROM Command Code. Driver set this field to represent what type command will be send to EEPROM device. 110 = read command 111 = erase command 101 = write command Write EEPROM Set to `1' to write EEPROM, it will be auto-cleared when AX88180 finishes the write operation. Read EEPROM Set to `1' to read EEPROM, it will be cleared when MAC finished the read operation. Driver can read PROMDPR register to get the returned data. Reload EEPROM Set to `1' to re-load EEPROM, this bit will be auto-cleared when AX88180 finishes loading operation. Reserved EEPROM Address Set this field to define the address for serial EEPROM access. (only support 16-bit data access, e.g. 93C56 type) R ROM_CMD R/W
11
ROM_WT
R/W
0
10
ROM_RD
R/W
0
9
ROM_RLD
R/W
0
8 7:0
R ROM_ADDR R/W
0 0x00
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AX88180
4.39 MAXRXLEN--Max. RX Packet Length Register Offset Address= 0xFCB8 Default = 0x0000_0600
Field 31:11 10:0 Name Type Default All 0's 0x600 Description Reserved Max RX Packet length This field defines the max length of received packet. It doesn't include 4-byte CRC. R RXLEN R/W
4.40 HASHTAB0--Hash Table0 Register Offset Address = 0xFCC0 Default = 0x0000_0000
Field 31:16 15:0 Name Type R HTAB0 R/W Default All 0's 0x0000 Description Reserved Hash table: bit15~bit0 Driver sets HASHTAB0, HASHTAB1, HASHTAB2 and HASHTAB3 to define 64-bit hash table. AX88180 will refer this table to check multicast packet if multicast filter is enabled (bit4 of RXFILTER) for RX. When AX88180 receives a packet then it extracts the destination address (DA). The DA is calculated by CRC32 algorithm. After the operation, AX88180 will grab the MSB[31:27] of result as hash table index. The range of index is from 0 to 63. For example, the hash table is composite as {HASHTAB3[15:0], HASHTAB2[15:0], HASHTAB1[15:0], HASHTAB0[15:0]}. If AX88180 detects the MSB[31:27] = 26 of CRC32 of DA for someone multicast packet, and driver set `1' to HASHTAB1[10], then the multicast packet will received by AX88180.
4.41 HASHTAB1--Hash Table1 Register Offset Address = 0xFCC4 Default = 0x0000_0000
Field 31:16 15:0 Name Type Default All 0's 0x0000 Reserved Hash table: bit31~bit16 Description R HTAB1 R/W
4.42 HASHTAB2--Hash Table2 Register Offset Address = 0xFCC8 Default = 0x0000_0000
Field 31:16 15:0 Name Type Default All 0's 0x0000 Reserved Hash table: bit47~bit32 Description R HTAB2 R/W
4.43 HASHTAB3--Hash Table3 Register Offset Address = 0xFCCC Default = 0x0000_0000
Field 31:16 15:0 Name Type R HTAB3 R/W Default All 0's 0x0000 Description Reserved Hash table: bit63 ~ bit48
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AX88180
4.44 DOGTHD0--Watch Dog Timer Threshold0 Register Offset Address = 0xFCE0 Default = 0x0000_FFFF
Field 31:16 15:0 Name Type R DOGTH0 R/W Default All 0's 0xFFFF Description Reserved Watch Dog Timer Low Word This register and DOGTHD1[11:0] are defined to an expired threshold for internal watchdog counter. The threshold {[DOGTHD1, DOGTHD0] is a 28-bit value. To multiply 28-bit value with one-cycle period of a host clock is the expired duration. If the DOGEN is set to `1' and WDTEI of ISR is set, then AX88180 will periodically generate interrupt whenever the counter reaches to the threshold.
4.45 DOGTHD1--Watch Dog Timer Threshold1 Register Address = 0xFCE4 Default = 0x0000_0000
Field 31:16 15 Name Type R DOGEN R/W Default Description All 0's Reserved 0 Dog Timer Enable 1 = Enable internal dog timer 0 = Disable All 0's Reserved 0x000 Dog Timer High Field. This field and DOGTHD0[15:0] combine to a 28-bit register.
14:12 11:0
R/W DOGTH1 R/W
4.46 SOFTRST --- Software Reset Register Address = 0xFCEC Default = 0x0000_0003
Field 31:2 1 0 Name Type R R/W RST_MAC R/W Default Description All 0's Reserved 1 Reserved 1 Software Reset enable Driver set this bit to `0' to reset MAC. The reset duration is depended on whenever this bit is de-asserted by driver. Most registers will be cleared to default value. 1 = in normal operation 0 = in reset status
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AX88180
5.0 Electrical Specification and Timings
5.1 DC Characteristics 5.1.1 Absolute Maximum Ratings
Symbol Description Rating Units TSTG Storage Temperature -40 to 150 C VCC3 Power supply of 3.3V -0.3 to VCC3 + 0.3 V VCC2 Power supply of 2.5V -0.3 to VCC2 + 0.3 V VI3 Input voltage of 3.3V IO with 5V tolerance -0.3 to 5.5 V VI2 Input voltage of 2.5V IO with 3.3V tolerance -0.3 to 3.9 V Note: Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability.
5.1.2 General Operation Conditions
Symbol Tj VCC2 VCC3 VI3 VI2 Description Junction temperature Supply Voltage of 2.5V Supply Voltage of 3.3V Input voltage of 3.3V IO with 5V tolerance Input voltage of 2.5V IO with 3.3V tolerance Min 0 2.25 3.0 0 0 Typ 2.5 3.3 3.3 2.5 Max 115 2.75 3.6 5.25 3.6 Units C V V V V
5.1.3 Leakage Current and Capacitance
Symbol IIN IOZ COUT CBID Description Input Leakage Current Tri-state leakage current Output capacitance Bi-directional buffer capacitance Min -10 -10 Typ 1 1 3.1 3.1 Max +10 +10 Units A A pF pF
5.1.4 DC Characteristics of 2.5V IO Pins
Symbol VCC2 Vil Vih Vol Voh Rpu Rpd Description Power supply of 2.5V IO Input low voltage Input high voltage Output low voltage Output high voltage Input pull-up resistance Input pull-down resistance Min 2.25 1.7 1.85 40 40 Typ 2.5 75 75 Max 2.75 0.7 0.4 190 190 Units V V V V V K K
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AX88180
5.1.5 DC Characteristics of 3.3V IO Pins
Symbol VCC3 Vil Vih Vol Voh Rpu Rpd Description Power supply of 3.3V IO Input low voltage Input high voltage Output low voltage Output high voltage Input pull-up resistance Input pull-down resistance Min 3.0 2.0 2.4 40 40 Typ 3.3 75 75 Max 3.6 0.8 0.4 190 190 Units V V V V V K K
5.1.6 Power Consumption
Device Only Measurement bases on 100MHz frequency of HCLK and turn on internal regulator at 25 oC temperature. Item Symbol Power-on with Operation at Operation at Operation at Stand-by current cable removed 1 2 VCC3 (IO) VCC3R 1.6 87 10Base-T 1.8 72 100Base-T 2.4 79 1000Base-T 2.5 105 (HCLK is off) 0.061 1.5 mA mA Units
Note: The current of VCC3R includes VCC2 core current.
5.1.7 Thermal Characteristics
A. Junction to ambient thermal resistance, Symbol
JA
Typ 46.3 Max Units o C/W
JA
Min -
B. Junction to case thermal resistance, Symbol
JC
Typ 16.2 Max Units o C/W
JC
Note:
Min -
JA , JC defined as below
=
JA
TJ - T A T - TC , JC = J P P
TJ: maximum junction temperature TA: ambient or environment temperature TC: the top center of compound surface temperature P: input power (watts)
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AX88180
5.2 A.C. Timing Characteristics 5.2.1 Host Clock
A. Reference clock (HCLK) Description Reference frequency Reference clock duty cycle B. Reference clock (CLK125) Description Reference frequency Reference clock duty cycle Min 40 40 Typ. 50 Max 100 60 Units MHz %
Min 45
Typ. 125 50
Max 55
Units MHz %
5.2.2 Reset Timing
HCLK R ST_N
T rst
Symbol Trst Reset pulse width Description Min 0.5 Typ. Max Units ms
5.2.3 Host Single Write Timing
Tsetup HCLK CSN
WEN
Tvalid_cycle
HA[15:1] Tar
Valid address
HD[31:0] Tad
Valid data
Symbol Description Tsetup CSN, WEN to HCLK setup timing Tar HA exceed to WEN timing Tad HA exceed to WEN timing Tvalid_cycle A Valid write cycle timing (synchronous to MCU) Tvalid_cycle A Valid write cycle timing- (asynchronous to MCU)
Min 2 0 0 4 6
Typ. -
Max -
-
-
Units ns HCLK HCLK HCLK HCLK
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AX88180
5.2.4 Host Burst Write Timing
H C LK CSN
H A [15:1]
A ddress T w en V alid data
A ddress + 4 T w en V alid data
A ddress + 8
V alid data
W EN
Symbol Twen
Description Valid write cycle timing
Min 6
Typ. -
Max -
Units HCLK
5.2.5 Host Single Read Timing
HCLK CSN/OEN Tac
HA[15:1]
Valid address Tovd Tdh Valid data
HD[31:0]
Symbol Tac Tac Tovd Tdh
Description CSN/OEN access timing (synchronous to MCU) CSN/OEN access timing (asynchronous to MCU) OEN assert to valid data timing Valid data hold timing to OEN de-asserted
Min 5 6 4 0
Typ. -
Max -
Units HCLK HCLK HCLK ns
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AX88180
5.2.6 Host Burst Read Timing
HCLK CSN Tac Address (A1) OEN Tac Address + 4 (A2) Tad Tac Address + 8 (A3) Tad
Tovd Invalid data Valid data (A1) Valid data (A2)
Tdh Valid data (A3)
Symbol Tac Tovd Tad Tdh
Description Valid address access timing OEN assert to valid data timing Burst mode address to valid data Valid data hold timing to OEN de-asserted
Min 6 4 4 0
Typ. -
Max -
Units HCLK HCLK HCLK ns
5.2.7 RGMII Clock Timing
Tcycle
Thi
Trising
Tfall
Tlo
Symbol Tcycle-1000 Thi-1000 Tlo--1000 Tcycle -100 Thi-100 Tlo-100 Tcycle -10 Thi-10 Tlo-10 Trising Tfall
Description Cycle timing for 1000Base-T High Timing for 1000Base-T Low timing for 1000Base-T Cycle timing for 100Base-T High Timing for 100Base-T Low timing for 100Base-T Cycle timing for 10Base-T High Timing for 10Base-T Low timing for 100Base-T Rising timing Fall timing
Min 7.2 3.6 3.6 32 16 16 320 160 160 -
Typ. 8 4 4 40 20 20 400 200 200 0.8 0.8
Max 8.8 4.4 4.4 44 22 22 440 220 220 -
Units ns ns ns ns ns ns ns ns ns ns ns
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AX88180
5.2.8 RGMII Receive Timing (1000/100/10 Mbps)
RXD[3:0] RXDV
RXCLK (at AX88180)
Thold Tsetup
Symbol Description Tsetup Setup timing to RXCLK (at AX88180) Thold Hold timing to RXCLK (at AX88180) Note: PHY adds the delay in RXCLK
Min 1.0 1.0
Typ. -
Max -
Units ns ns
5.2.9 RGMII Transmit Timing
T sk ew
T X C X (a t A X 8 8 1 8 0 )
T X D [3 :0 ] TXEN
T X C X ( a t P H Y in te r n a l)
T d e a ly T d e la y
Symbol Description Tskew Data to clock TXCX skew Tdelay Data to clock in PHY site Note: PHY needs to add delay in TXCX
Min -500 1.5
Typ. 0
Max +500 2.0
Units ps ns
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AX88180
5.2.10 MDIO Timing
Tclk
MDC
MDIO (output) Tod MDIO (input) Ts Th
Symbol Tclk Tod Ts Th
Description MDC clock timing* MDC falling edge to MDIO output delay MDIO data input setup timing MDIO data input hold timing
Min
Typ. 1340 -
Max 32 -
Units ns ns ns ns
10 4
5.2.11 Serial EEPROM Timing
T c lk
EECLK
EEDI (o u tp u t) Tod EEDO (in p u t) Ts T scs Th T hcs T lc s
EECS
Symbol Tclk Tod Ts Th Tscs Thcs Tlcs
Description EECLK clock timing* EECLK falling edge to EEDI output delay EEDO data input setup timing EEDO data input hold timing EECS output valid to EECLK rising edge EECLK falling edge to EECS invalid timing Minimum EECS low timing
Min
Typ. 1370 -
Max 5 -
Units ns ns ns ns ns ns ns
6 6 650 0 -
560
-
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AX88180
6.0 Package Information
He E A A2
A1
Hd
D
pin 1
b
e
SYMBOL MIN.
A1 A2 A b D E e Hd He L L1 0 15.85 15.85 0.45 0.13 13.90 13.90 0.05 1.35
MILIMETER NOM
0.1 1.4 1.45 1.6 0.18 14.00 14.00 0.40 16.00 16.00 0.60 1.00 7 16.15 16.15 0.75 0.23 14.10 14.10
MAX
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L
L1
AX88180
7.0 Ordering Information AX88180 Product name L Package LQFP F F: Lead Free
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AX88180
Appendix A1. 16-bit mode address and data bus
A1-1. 16-bit mode and separated address and data bus
Note: The name of control signal for MCU is demonstrated only.
A1-1-1. AX88180 is synchronous to host MCU
G e n e ric M C U /C S x /R D /W R CLK A [1 5 :1 ] D [1 5 :0 ] /IN T x /R E S E T A X 88180 CSN OEN W EN HCLK H A [1 5 :1 ] H D [1 5 :0 ] IN T N R ST_N H D [3 1 :1 6 ] N o te : flo a tin g 4 .7 K 3 .3 V
G P IO 0
A1-1-2. AX88180 is asynchronous to host MCU
Note: For asynchronous mode, system must provide extra OSC to output clock to AX88180
OSC 3 .3 V A X 88180 CSN OEN W EN HCLK A [1 5 :1 ] D [1 5 :0 ] /IN T x /R E S E T H A [1 5 :1 ] H D [1 5 :0 ] IN T N R ST_N H D [3 1 :1 6 ] N o te : flo a tin g G P IO 0 4 .7 K
G e n e ric M C U /C S x /R D /W R
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AX88180
A1-2. 16-bit mode multiplexed address and data
A X 88180 /C S x /R D /W R BCLK ALE A D [1 5 :0 ] H D [1 5 :0 ] /IN T x /R E S E T IN T N R ST_N H D [3 1 :1 6 ] N o te : F lo a tin g A d d r[1 5 :1 ] L a tc h CSN OEN W EN HCLK H A [1 5 :1 ] G P IO 0 3 .3 V
4 .7 K
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ASIX ELECTRONICS CORPORATION
AX88180
Appendix A2. 32-bit mode address and data bus
A2-1. Linear address mode and byte aligned (in synchronous mode)
G e n e ric M C U /C S x /R D /W R CLK A [1 5 :1 ] D [3 1 :0 ] /IN T x /R E S E T A X 88180 CSN OEN W EN HCLK H A [1 5 :1 ] H D [3 1 :0 ] IN T N R ST_N
F lo a tin g , if n o u s e
G P IO 0
Note: For asynchronous mode, system must provide extra OSC to output clock to AX88180. Please refer to Section A1-1-2 for details.
A2-2. MCU is double-word boundary and the addressing is DWORD unit
G e n e ric M C U /C S x /R D /W R CLK A [1 3 :0 ] D [3 1 :0 ] /IN T x /R E S E T A X 88180 CSN OEN W EN HCLK H A [1 5 :2 ] H D [3 1 :0 ] IN T N R ST_N
HA1 G ro u n d F lo a tin g , if n o u s e
G P IO 0
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AX88180
Appendix A3. AX88180 with Giga-PHY Connection
A X 88180 rx d [3 :0 ] rx d v rx c lk col c rs m d io m dc p h y in tn tx d [3 :0 ] tx e n tx c lk tx c x c lk 1 2 5 GTXCLK G ig a -M A C G ig a -P H Y 88E1111 rx d [3 :0 ] rx _ d v rx _ c lk col c rs m d io m dc IN T n tx d [3 :0 ] tx _ e n tx _ c lk G TX _C LK 1 2 5 c lk
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AX88180
Appendix A4. Synchronous and asynchronous timing selection
AX88180 can support synchronous or asynchronous access from host MCU. Below information provides some references to select clock frequency of host MCU and AX88180.
A4-1. AX88180 is synchronous with host MCU.
The timing selection is suitable for both 32-bit and 16-bit mode.
Frequency Max 100MHz
Access type Single or Burst
Valid access timing (OEN/WEN active timing) Min 5 clocks
A4-2. AX88180 is asynchronous to host MCU.
The timing selection is suitable for both 32-bit and 16-bit mode.
Frequency Max 100MHz
Access type Single or Burst
Valid access timing (OEN/WEN active timing) Min 6 reference clocks (Note)
Note: The reference clock is from OSC, and it's not the output of host MCU. For instance, if AX88180 runs in asynchronous mode and refers a 100MHz clock from OSC, whereas MCU runs in 125MHz environment. In such condition, MCU must at least offer 60ns (min 6 reference clock of 100MHz) access timing to AX88180. The 60ns for MCU is almost reached to 8 clocks (125MHz). We recommend that it is needed to extend the access timing of MCU to AX88180.
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AX88180
Appendix A5. Wake On LAN (WOL) without driver via Magic Packet
A5-1. Wake On LAN (WOL) without driver
AX88180 can support WOL without driver exists. In such situations, system must offer 3.3V voltage, reference clock and rest signal to AX88180. Whenever AX88180 detects magic packet from cable, it will drive WAKEUP signal to host system. AX88180 defaults in MII interface (after reset before EEPROM auto-loaded). Hence if Giga-PHY supports RGMII interface, designer must use EEPROM to set AX88180 to RGMII interface. Users must take care is that AX88180 only supports delay timing of RGMII (refer to 5.2.8), thus it must add extra delay (at least 0.7ns) in PCB board if system needs WOL and without running driver. Below diagram is shown the concept.
No power area OSC AX88180 Delay line HCLK MCU Data Addr CSN/OEN/WEN Rst_n rxclk rxclk Giga-PHY
Power RC circuit or Reset pulse generator
Another available method is to set Giga-PHY in MII mode (by configure pin, if Giga-PHY has this feature). After AX88180 detects magic packet and wakes up system, driver can set AX88180 to RGMII mode and also set Giga-PHY to RGMII mode by MDIO interface. If designer employs this approach, the delay timing issue is not needed.
A5-2. Magic packet
The magic packet received by AX88180 is shown as following; DA + SA + 0x0000 + 0xFFFFFFFFFFFF + (at least repeats 16 times) DA + CRC32 DA = MAC address of AX88180 (6 bytes) SA = Source address (6 bytes)
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AX88180
Revision History
Revision V1.0 V1.0A Date 2005/10/4 2006/3/31 Comment First edition 1. Correct some typos in Section 3.4. 2. Correct the name definition of some pins in Section 1-3 and Section 2. V1.1 2006/7/28 1. Some typo errors corrected between Pin diagram and tables. 2. Host read/write timing revised in Section 5. 3. Some bits of registers are updated. 4. Add some connections between MCU and AX88180 in Appendix. 5. Add wake up LAN in Appendix. 6. Update the power consumption information in Section 5.1.6. V1.2 2007/3/28 1. Correct some information in Section 3.9 for 16-bit mode operation. 2. Modify the data access timing information in Section 5.2.5, 5.2.6 and Appendix A4. 3. Update the power consumption information in Section 5.1.6. 4. Add some information in Section 3.10. 5. Define the bit filed name (RXJUBOLEN) for bit 10:7 of MAC_CFG1 register. 6. Add AX88180 with Gigabit PHY Connection information in Appendix A3. 7. Modify some descriptions in Section 1.1, 4.6, 4.16, 4.17, 4.18, 4.22, 4.34~4.36, 4.40. 8. Modify the description of TXCLK and GTXCLK pin in Section 2.2. 9. Rearrange the content of Appendix into Appendix A1~A5. 10. Change the number format from 16h'XXXX to 0xXXXX for example. V1.3 2007/5/4 1. 2. V1.4 2007/5/18 Swap the pin definition of pin #90 and #91 in Section 2.6 and Figure 2. Correct some typo errors of pin type in Table 1 and Table 5.
1. Modify max operation frequency of HCLK from 125MHz to 100MHz. 2. Modify some thermal information in Section 5.1.7.
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AX88180
4F, No.8, Hsin Ann Rd., Hsinchu Science Park, Hsinchu, Taiwan, R.O.C. TEL: +886-3-5799500 FAX: +886-3-5799558 Email: support@asix.com.tw Web: http://www.asix.com.tw
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